Open SoC Debug

Building blocks for your SoC debug infrastructure

About

Open SoC Debug is a new project co-managed by the OpTiMSoC and lowRISC projects with the mission to establish a repository of common SoC debug components. While our original focus is on hardware building blocks and their interface on the debug host, we highly welcome debug software developers to broaden the scope of Open SoC Debug.

News

  • (2017-09-21) Major changes in Open SoC Debug ahead! Over the last roughly two years, Open SoC Debug has grown into a reliable debugging tool for the needs of lowRISC and OpTiMSoC. A lot of effort went into fixing small bugs to improve reliability and to add some features such as the emulated UART device, UART-DEM. And it was worth the effort, as we’ve seen over the summer when we added Linux support to OpTiMSoC. Control flow traces generated by the CTM modules, as well as the UART-DEM module were major enablers for this work. Read more
  • (2017-03-21) Documentation updated We have updated our specification and other documentation significantly! Read more
  • (2016-10-26) ORCONF Stefan Wallentowitz gave an overview talk of the Open SoC Debug project at ORCONF. Please find a recording of the talk on youtube.
  • (2016-09-02) lowRISC release We have migrated the OpTiMSoC debug structure to use the Open SoC Debug prototype implementation. Learn more about it and get started with the tutorial in the user guide.
  • (2016-07-15) lowRISC release We finished prototyping of the first full Open SoC Debug-based lowRISC SoC. There is a comprehensive tutorial that includes documentation details. Read more

Goals

  • Specification of a unified infrastructure for SoC run-control and trace debugging
  • Provide a collection of generic hardware debug components
  • Integrate the host interface and host-target transfer hardware

We are still at early phases of Open SoC Debug. Please feel free to contact us if you are interested in the project or want to participate or join our mailing list: